A decoupling capacitor may be used as a low-impedance source of current to minimize supply voltage fluctuations caused by rapid switching of the active devices. One parameter affecting the performance of decoupling capacitors in high speed digital systems is the parasitic inductance associated with the current loop formed by the multilayer capacitor's internal electrodes and their connection to the board's power planes. The greater the inductance the slower the speed with which the system can operate. This loop inductance is a function of several variables including, for example, capacitor size, capacitor terminal configuration, capacitor bottom cover layer thickness, vertical distance from power planes to board surface, via count, via diameter, via separation, horizontal offset of vias from device pad, and etch configuration of the surface layer.
The inductance of a two-terminal capacitor can generally be minimized by locating the vias that connect to the power planes as close as possible to one another, but it is still generally on the order of one nanohenry. A need, therefore, exists for a technique for further minimizing the connection inductance associated with decoupling capacitors.